1. Field of the Invention
The present invention relates to a semiconductor apparatus.
2. Description of the Related Art
A semiconductor apparatus such as an IC (Integrated Circuit) or an LSI (Large-Scale Integration) generally provided with an ESD protection circuit on the inside thereof and the outside thereof in order to prevent breakdown caused by ESD (Electro-Static Discharge). Especially, the ESD protection circuit provided on the inside of the semiconductor apparatus is mainly intended for prevention of ESD breakdown during handling before the semiconductor apparatus is mounted onto a circuit board.
For example, FIG. 13 of Japanese Laid-Open Patent Publication No. 2005-93496 discloses an ESD protection circuit (power supply terminal protection circuit) that includes an RC delay circuit, an inverter (inverting circuit), and an NMOS (N-channel Metal-Oxide Semiconductor) transistor. In the ESD protection circuit, a connection point between a resistor and a capacitor making up the RC delay circuit is connected through the inverter to a gate of the NMOS transistor for clamping a power supply terminal VDD and a ground terminal GND. If a surge voltage, which is positive on the side of the power supply terminal VDD, for example, is generated due to ESD, the NMOS transistor is kept ON during a period corresponding to a time constant of the resistor and the capacitor, so that the surge voltage is prevented from flowing through internal circuits other than the ESD protection circuit.
For example, FIG. 3 of Japanese Laid-Open Patent Publication No. 2007-142423 discloses an ESD protection circuit in which an RC-filter (corresponding to the RC delay circuit of Japanese Laid-Open Patent Publication No. 2005-93496) and an NMOS transistor are connected via three inverters connected in series. In the ESD protection circuit, the two inverters added to the ESD protection circuit make up a pre-driver that buffers an input to a gate of the NMOS transistor.
As such, the NMOS transistor is kept ON during a period corresponding to the time constant of the resistor and the capacitor, so that the surge voltage can be released, and thus the internal circuits of the semiconductor apparatus can be protected from the ESD breakdown.
In the ESD protection circuit as described above, the NMOS transistor is OFF at the time of energization while a power supply voltage is applied to the semiconductor apparatus, so that a malfunction is prevented. However, when the power supply voltage is not stable and changes, the NMOS transistor may be turned on as is the case with the ESD surge depending on a relationship between the abruptness of such a voltage change and the time constant of the resistor and the capacitor.
Therefore, the instantaneous change of the power supply voltage caused by noise, etc., may cause a malfunction of the semiconductor apparatus. Especially, in the case of a power supply IC for supplying power to other circuits, this problem may become prominent since stable power may not be supplied.